Sunday, 11 December 2011

AMD Phenom

Phenom (pronounced /fɨˈnɒm/, as in the chat phenomenon) is the 64-bit AMD desktop processor band based on the K10 microarchitecture,1 in what AMD calls ancestors 10h (10 hex, i.e. 16 in accustomed decimal numbers) processors, sometimes afield alleged "K10h". Triple-core versions (codenamed Toliman) accord to the Phenom 8000 alternation and cloister cores (codenamed Agena) to the AMD Phenom X4 9000 series. The aboriginal processor in the ancestors was appear in 2007.

Background

AMD considers the cloister amount Phenoms to be the aboriginal "true" cloister amount design, as these processors are a caked multi-core architecture (all cores on the aforementioned silicon die), clashing Intel's Amount 2 Cloister alternation which are a multi-chip bore (MCM) design. The processors are on the Socket AM2+ platform.2

Before Phenom's aboriginal absolution a blemish was apparent in the adaptation lookaside absorber (TLB) that could account a arrangement lock-up in attenuate circumstances; Phenom processors up to and including dispatch "B2" and "BA" are afflicted by this bug. BIOS andcomputer application workarounds attenuate the TLB, and about acquire a achievement amends of at atomic 10%.3 This amends was not accounted for in pre-release previews of Phenom, appropriately the achievement of aboriginal Phenoms delivered to barter is accepted to be beneath than the examination benchmarks. "B3" dispatch Phenom processors were appear March 27, 2008 after the TLB bug and with "xx50" archetypal numbers.4

An AMD accessory has appear a application for the Linux kernel,5 to affected this bug bycomputer application appetite of accessed- and dirty-bits. This adjustment causes beneath achievement accident than antecedent workarounds. The affairs was said in December 2007 to accept accustomed "minimal funtional testing."67

AMD launched several models of the Phenom processor in 2007 and 2008 and an upgraded Phenom II in backward 2008

Phenom X4

Agena (65 nm SOI)

Four AMD K10 cores

L1 cache: 64 KB + 64 KB14 (data + instructions) per core

L2 cache: 512 KB per core, full-speed

L3 cache: 2 MB aggregate amid all cores

Memory controller: bifold approach DDR2-1066 MHz with unganging option

MMX, Extended 3DNow!, SSE, SSE2, SSE3, SSE4a, AMD64, Cool'n'Quiet, NX bit, AMD-V

Socket AM2+, HyperTransport with 1600 to 2000 MHz

Power burning (TDP): 65, 95, 125 and 140 Watt

First release

November 19, 2007 (B2 Stepping)

March 27, 2008 (B3 Stepping)

Clock rate: 1800 to 2600 MHz

Models: Phenom X4 9100e to 9950

Phenom X3

Toliman (65 nm SOI)

Three AMD K10 cores

L1 cache: 64 KB abstracts and 64 KB apprenticeship accumulation per core

L2 cache: 512 KB per core, full-speed

L3 cache: 2 MB aggregate amid all cores

Memory controller: bifold approach DDR2-1066 MHz with unganging option

MMX, Extended 3DNow!, SSE, SSE2, SSE3, SSE4a, AMD64, Cool'n'Quiet, NX bit, AMD-V

Socket AM2+, HyperTransport with 1600 to 1800 MHz

Power burning (TDP): 65 and 95 Watt

First release

March 27, 2008 (B2 Stepping)

April 23, 2008 (B3 Stepping)

Clock rate: 2100 to 2500 MHz

Models: Phenom X3 8250e to 8850